This invention is related to operational amplifiers, and in particular to operational amplifiers to use as interstage amplifiers for analog-to-digital converters, in particular low-voltage low-power pipeline analog-to-digital converters.
Analog-to-digital converters (ADCs) with pipeline architecture are well suited for low-power, high-speed applications, for example for inclusion in integrated circuits such as CMOS integrated circuits. Advantages of the pipeline architecture over other architectures for high-speed applications include small die-area and low-complexity. CMOS technology is well established and offers the advantages of high levels of integration and low fabrication costs. CMOS can be used for both analog and digital functions, often on the same device.
Designing such pipeline ADCs for very low power and deep sub-micron CMOS digital processes is a challenge due mostly to reduced dynamic range and low supply voltage, e.g. 2.5V, while maintaining signal-to-noise ratio (SNR) and signal-to-noise and distortion ratio (SINAD). For example, with low supply voltage, the threshold voltages of the MOS devices used in analog circuits such as amplifiers used in a pipeline ADC can constrain the designs.
FIG. 1 shows a block diagram for a typical pipeline ADC 100. While ADC 100 of FIG. 1 is labeled prior art, a pipeline ADC conforming to the architecture of FIG. 1 and having one or more features of the invention described herein may not be prior art. Pipeline ADC 100 produces an N-bit number BNxe2x88x921, . . . , B1, B0 and comprises a number, say K, of stages, shown numbered (Kxe2x88x921), (Kxe2x88x922), . . . , 1, 0 in FIG. 1, with each stage responsible for resolving one or more bits. Each stage need not be identical. For example, each stage may be responsible for resolving a different number of bits. For simplicity, all stages but the last are assumed identical. Each stage produces a digital output and an analog residue output. The digital outputs of stages (Kxe2x88x921), (Kxe2x88x922), . . . , 1, 0 are respectively labeled PKxe2x88x921, PKxe2x88x922, . . . , P1, P0 in FIG. 1 The stages may all produce a digital output with the same number of bits, or a digital output with an unequal number of bits. The digital output PKxe2x88x921, PKxe2x88x922, . . . , P1, P0 are input to a code converter to produce the N-bit output BNxe2x88x921, . . . , B1, B0. The analog residue signal produced by each stage but the last is input to the next stage.
One example is a xe2x80x9c1.5-bitxe2x80x9d per stage converter. One bit is resolved at each stage, with the resulting analog residue passed along to the next stage for resolution of another bit. The digital output in such an example, the final stage might be a two-bit flash ADC that resolves the two least significant bits. In one example, such an architecture includes Nxe2x88x922 stages and one two bit ADC for the final stage for an N-bit converter. The code output by each stage may a three value output (e.g., a signal having value of xe2x88x921, 0, or +1) or two binary output signals, called the full bit and half bit outputs.
FIG. 2 shows one architecture for an intermediate stage, say the M""th stage 200 of ADC 100. While ADC 200 of FIG. 1 is labeled prior art, a pipeline ADC conforming to the architecture of FIG. 2 and having the features of the invention described herein may not be prior art. ADC 200 includes a sample and hold (S/H) circuit 203 to sample the residue from the previous stage, an analog-to-digital converter (ADC) 205 that determines the digital code PM for this stage, a digital-to-analog converter (DAC) 207 that produces an analog equivalent of PM, denoted VDAC(M), and a summing interstage amplifier 209 that subtracts the analog equivalent VDAC(M) from the sampled previous-stage residue to produce the residue VRES(M) that is fed to the next stage. In general, summing interstage amplifier 209 also multiplies the difference by a factor of 2J, where J is the integer part of the number of bits resolved at each stage. For a 1.5 bit stage of an N-bit converter with a 2-bit flash converter as the last stage, J is 1, so that the interstage amplifier outputs
VRES(M)=2(VRES(M)xe2x88x92VDAC(M))
for M=Nxe2x88x921, . . . , 2.
The interstage amplifier 209 may be implemented by a switched capacitor circuit that includes a fully differential operational amplifier. One such switched capacitor circuit incorporates the sample and hold for the next stage, so that a separate sample and hold circuit 205 is not necessary except for the first stage.
For relatively high speed and low settling time operation, the operational amplifier needs to have a very high gain-bandwidth product. One mechanism for achieving high gain is a vertical gain enhancing technique such as cascading. Cascoding, however, is relatively unsuitable for low voltage operation because, for example, threshold voltages are a significant fraction of the process supply voltage for deep sub-micron technologies, and there is insufficient supply voltage for the additional voltage drop across the cascode transistor. Another alternative for the operational amplifier is a cascaded set of differential amplifiers.
There is therefore a need for a cascaded operational amplifier for use in stages of a pipeline ADC that achieves a relatively high speed, e.g., 80 megasamples per second (Ms/s), a relatively low settling time, and that has relatively low power consumption with a low supply voltage.
Such a low-power operational amplifier may have limited dynamic range. For example, the output voltage swing may be limited, and with a low supply voltage, the common mode voltage of the amplifier (called the xe2x80x9cinherentxe2x80x9d common mode voltage) may vary by a significant fraction of the supply voltage. One way to overcome this is by careful control of the inherent common mode voltage of each of the cascaded differential amplifiers. FIG. 3A shows a typical CMOS differential amplifier 300 with common mode control circuitry 305. Common mode control circuitry 305 typically requires a common mode current source in a feedback configuration, which may require one or more operational amplifiers, and thus itself consumes power. There typically is one such common mode control for the operational amplifier that includes the cascade of differential amplifiers. See U.S. Pat. No. 4,918,399 to Devecchi, et al. entitled xe2x80x9cCOMMON MODE SENSING AND CONTROL IN BALANCED AMPLIFIER CHAINSxe2x80x9d for an example of common mode control circuitry that controls the common mode voltage of a set of cascaded differential amplifiers.
An alternate CMOS differential amplifier 330 is shown in FIG. 3B. Differential amplifier 330 includes its own local common mode feedback circuit in the form of resistive-averaged common mode feedback. Two equal sized resistors 333 of resistance R are placed between the two outputs and explicitly generate the inherent common mode voltage VCM-AMP at their connecting node 335. The connecting node 335 is connected to the commonly connected gates of transistors M1 and M2. The approximate gain of the differential amplifier is set by the product of the transconductance, gm, of transistor M3, and the parallel combination of the output impedance of M1, M3, and the resistor of value R. Thus, differential amplifiers with different R values have different gains.
The output voltage swing of amplifier 330 is limited to about two threshold voltages. There thus is a difficulty of using such resistive common mode feedback amplifiers in the operational amplifier of the stages of a pipeline ADC that has a low supply, voltage. In particular, the maximum and minimum output voltages of the differential amplifiers need to match the maximum and minimum references of the ADC to maximize the dynamic range.
There thus is a need for controlling the one or more reference voltages for the stages of a pipeline ADC relative to the inherent common mode voltages of the operational amplifiers in the stages. In particular, for operational amplifiers that include q cascade of differential amplifiers that each have their own common mode feedback, i.e., that each use resistive-common mode feedback, there is a need for controlling the one or more reference voltages for the stages of a pipeline ADC relative to the inherent common mode voltages of the operational amplifiers. There thus is a need for a method and apparatus for supplying one or more reference voltages to the stages of a pipeline ADC that provide for using an operational amplifier that has a limited dynamic range.
Wireless local area networks offer many advantages over wired local area networks. One advantage is the use with portable devices such as portable computers, personal digital assistants, and other devices. One desirable property of circuits for operation with portable devices is low power consumption.
The IEEE 802.11a standard has been established for operation in the UNII bands (5 GHz range) at 54 MBPS. Single-chip radio transceivers are now being promoted by several companies that conform to the IEEE standard, e.g., Atheros Communications (Sunnyvale, Calif.) which markets its AR5000 chipset. Such chipsets put complete 5.15-5.35 GHz transceivers on a chip, and need only few external filters, a transmit/receive switch and a crystal to operate. Makers like Atheros and Radiata Communications (San Jose, Calif., acquired by Cisco Systems, Inc., the assignee of the present invention) produce single-chip radio transceiver devices that operate at low signal power-output levels. Such companies also are designing single-chip modems for operation with the single-chip transceivers and conforming to the IEEE 802.11a standard. See the First Parent Application. Such a modem generates the analog signal for transmission by the transmitter part of the transceiver, and also accepts the analog signal from the receiver part of the transceiver. The receive path includes digitizing the received signal using an analog-to-digital converter.
There is thus a need for an ADC that can be incorporated in a modem chip, that operates with relatively low power, and that provides for the modem to conform to the standards such as the IEEE 802.11a standard.
For more information on the IEEE 802.11a standard, see: (1) Draft Supplement to Standard, For Telecommunications and Information Exchange Between Systemsxe2x80x94LAN/MAN Specific Requirementsxe2x80x94Part 11: Wireless Medium Access Control (MAC) and physical layer (PHY) specifications: High Speed Physical Layer in the 5 GHz band. {P802.11a/D7.0 July 1999}; (2) Draft Standard for Information technologyxe2x80x94Telecommunications and information exchange between systemsxe2x80x94Local and metropolitan area networksxe2x80x94Specific requirementsxe2x80x94Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications {ANSI/IEEE Std 802.11, 1999}; and (3)http://www.manta.ieee.org/groups/802/11/.
Disclosed herein is an operational amplifier suitable for use in a pipeline analog-to-digital converter (ADC). The operational amplifier includes a cascaded chain of differential amplifiers, each differential amplifier including resistive-averaged common mode feedback to produce an inherent common mode voltage for the differential amplifier, a particular differential amplifier of the chain having the highest gain of the gains of the differential amplifiers. The operational amplifier has one or more feedback paths each including a compensation capacitor to compensate the operational amplifier. Also included are one or more switches controlled by a control signal to switch on or off the differential amplifiers of the chain other than the highest-gain differential amplifier of the chain such that the power consumption of the operational amplifier is reduced by turning off the differential amplifiers other than the highest-gain differential amplifier while the dynamic response of the operational amplifier is not compromised by the highest-gain differential amplifier being turned on or off.